The structure of a memory chip, of a microchip having a multilayer design or of a processor as a three-dimensional structure is referred to as topography and is applied for at the utility models office of the German Patent and Trademark Office (DPMA).
Such structures are able to be protected, particularly when they, as ASICs, are the hardware version of a software patent. A topography ("mask-work" in the USA, "integrated circuit topographies" = ICTs in Canada) is only able to be protected when it has characteristic property ("Eigenart"); a comparable qualitative obstacle far-removed from the inventive step of the utility model, without explicitly requiring novelty.